Mapping to Reduce Contention in Multiprocessor Architectures
Abstract
Reducing communication overhead has been widely recognized as a
requirement for achieving efficient mappings which substantially
reduce the execution time of parallel algorithms. This paper presents
an iterative heuristic for static mapping of parallel algorithms to
architectures. Special attention is given to measuring and reducing
channel contention. Experimental results are used to show the effects
of channel contention for packet-switched networks and the improvement
realized by our heuristic. We also present preliminary results for
wormhole-routed networks.
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Last updated by Loren Schwiebert Email: 
on Jun-06-2001